The invention relates to making new structures for semiconductor components, and in particular SOI (silicon on insulator), or more generally semiconductor on insulator structures.
As illustrated in FIG. 5A, SOI structures (and more generally semiconductor on insulator structures) are stacks made up of a superficial film 20 made from monocrystalline silicon (semiconducting material, respectively), a dielectric layer 3, in general silicon oxides, and a support substrate 2, e.g. silicon. These SOI structures are for example obtained through assembly by molecular adhesion of a surface oxidized silicon plate, with another silicon plate, then thinning the first substrate.
More precisely, the assembly comprises a step for preparing the surface of the two plates, a contacting step, and a thermal treatment step. Traditionally, this thermal treatment is done at temperatures typically between 900° and 1250° C. for 2 h.
Then, at least one of the two plates is thinned, allowing a thin semiconductor layer 20 to remain on a dielectric layer 3.
The thinning occurs through different mechanical, or chemical, means, or by separation at an embrittled buried layer, for example by implanting gaseous species (e.g. hydrogen).
For certain applications, it is interesting to obtain circuits on a conducting ground plane 4 (FIG. 5B).
To that end, one seeks to have the assembly formed by the superficial semiconducting layer 20 and the buried dielectric layer 3 arranged on an electrically conducting layer, or ground plane (FIG. 5B). In this way, it is possible to control the density of the carriers in the semiconductor layer near the interface via the potential difference applied to the buried conducting layer and the semiconducting layer.
However, it is difficult to obtain SOI plates with a dielectric layer 3 having a small thickness, e.g. less than 150 nm, and a ground plane.
One of the methods used by SOI substrate users is the ion implantation of the final SOI substrate through the film 20 and the electrically insulating layer 3 to dope the semiconducting material of the substrate so as to obtain a conducting layer situated at the interface between the dielectric layer and the final substrate.
Ideally, to have a ground plane, it is necessary to implant the substrate, through the surface film 20 and the insulator layer 3, so as to have doping greater than 1019 at·cm−3, preferably greater than 1020 at·cm−2, for example 1021 at·cm−3. However, obtaining this optimum poses a problem, as the use of fairly significant ion implantation (in the vicinity of 1016 at·cm−2 or 1015 at·cm−2), to obtain such doping under the oxide layer 3, leads to degradation of the layers passed through, i.e. doping and degradation of the superficial semiconductor layer 20 and the electrically insulating layer 3. This has an impact on the performance of the superficial layer, in which components must be made, e.g. transistors (this layer can in particular serve as a channel for transistors). To offset this phenomenon, it is common for the implantation doses to be reduced, to ultimately obtain doping close to 1018 at·cm−3, below the optimal conditions. This under-dosed implantation limits (but does not eliminate) the degradations of the layer 20.
The problem therefore arises of making a SOI semiconducting structure having a ground plane between the dielectric layer and the final substrate, the two upper layers, superficial layer of semiconducting material and dielectric material not being degraded by the formation of said ground plane.
The problem also arises of achieving the optimal doping to form the ground plane.